AR# 64775

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UltraScale DDR3 - tZQinit violations seen during DDR3 simulations

描述

Version Found: DDR3 v7.1

Version Resolved: See (Xilinx Answer 69036)

The following tZQinit violations might be seen during DDR3 simulations when using the Micron memory model:

# sim_tb_top.mem_model_x8.memRank[0].memModel[1].u_ddr3_x8.chk_err: at time 5544836.0 ps ERROR: tZQinit violation during Activate

# sim_tb_top.mem_model_x8.memRank[0].memModel[0].u_ddr3_x8.main: at time 5533970.0 ps ERROR: TZQinit violation during ODT transition

解决方案

These violations are the result of an issue with the Micron memory model and not the MIG IP.

These violations can be safely ignored because the violations will not occur during hardware.

Please contact Micron for a solution with their memory model.

Revision History:

06/30/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 64775
日期 01/02/2018
状态 Active
Type 已知问题
器件
Tools
IP
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