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UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.2) - PCIe link Up failure due to deassertion of CPLLLOCK during reset
Version Found: 4.0 (Rev. 1)
Version Resolved and other Known Issues: (Xilinx Answer 57945)
On KU ES1/ES2 and VU ES1 devices, an intermittent link training issue has been seen due to an issue with the CPLL calibration module.
This is a known issue and will be fixed in Vivado 2015.3.
There are two patches for Vivado 2015.2, attached to this answer record.
Both patches must be applied to fix the issue.
Please install the patches as described below.
- The provided patches are for Vivado 2015.2.
- Unzip the attached zip files to the directory of your choice.
- Open Vivado 2015.2 and create a new project.
- Open IP catalog. Right click the core you are using and choose IP Settings.
- Click Add Repositories and point it to the location where you have unzipped the patch.
- Click OK. You are now ready to generate the core.
- If you have previously generated the core, you can choose 'Upgrade IP' on your core.
- Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.
After the patches are installed,
- The version of the UltraScale FPGA Gen3 Integrated Block for PCI Express core should indicate: v4.0 (Rev. 2)
- When the GT instantiation is selected in the project source tree, it should point to the instance in the IP catalog which has the repository set to the location where the GT Wizard patch is.
Note: "Version Found" refers to the version the problem was first discovered.
The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/10/2015 - Initial Release
- UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)