AR# 64983

Vivado IP Integrator - How to generate a testbench for the Block Diagram (BD)

描述

This Answer Record demonstrates how to use the testbench generator tool in the Design Utilities in the Xilinx TcL store, which provides a clock and reset stimulus.

解决方案

To use this utility, go to Tools -> Xilinx Tcl Store, and select Refresh.

Once, the refresh is done. Install Design Utilities 1.17 (or later):

 

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Open your Block Design (BD), and run the Tcl command below to generate the testbench:

tclapp::xilinx::designutils::write_ip_integrator_testbench -addToProject
AR# 64983
日期 08/28/2015
状态 Active
Type 综合文章
Tools