Version Found: DDR4 v1.0, DDR3 v1.0
Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036) for DDR3
The XCZU2EG and XCZU3EG devices with the SBVA484 package only have 2 HP banks available.
As a result, there are not enough available I/O to support DDR4 and DDR3 DIMMs.
However, the DDR4/DDR3 IP GUI still shows DIMMs available but with a limited data width up to 32-bits.
Do not select a DIMM with a reduced data width for the XCZU2EG and XCZU3EG devices with the SBVA484 package as DIMMs are not supported for the device/package combinations.
The DIMMs will be removed from the IP GUI in a future release to prevent confusion.
Revision History:
09/30/2015 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| AR# 65083 | |
|---|---|
| 日期 | 01/02/2018 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |
| IP | |