UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65154

LogiCORE IP DisplayPort - What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register?

描述

What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register?

解决方案

The HSYNC_WIDTH register (0x050) is documented in the DisplayPort Sink Core Configuration Space section of the DisplayPort Product Guide (PG064).

The default HSYNC_WIDTH is set to the max of 16 clocks.

The default configuration should cover most use cases, but if the user application requires, it can be reduced by updating the HSYNC_WIDTH register.

The DisplayPort core does not have a VSYNC_WIDTH register.

The VSYNC_WIDTH is fixed to 64 clocks.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54522 LogiCORE IP DisplayPort -面向 Vivado 2013.1 和更新工具版本的版本说明和已知问题 N/A N/A
AR# 65154
日期 08/07/2015
状态 Active
Type 综合文章
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • DisplayPort
的页面