We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6535

ModelSim VLOG - ERROR: ../../../<design>.v: Port 'OUT' not found in module


Keywords: LogiBLOX, ModelSim, Vlog, Verilog

Urgency: Standard

General Description:
When I perform a functional simulation of a LogiBLOX-generated Verilog module, the following error messages are reported:

ERROR: ../../../<design>.v: Port 'OUT' not found in module
ERROR: ../../../<design>.v: Port 'IN1' not found in module


This is generally a result of using incompatible simulation libraries with the LogiBLOX module. Specifically, if the LogiBLOX module was created by version 1.5i (or earlier) of the Alliance or Foundation software, and you are simulating with the 2.1i (or later) version of the SimPrim libraries, these errors will occur.

This happens because the port names have been changed from the previous versions of the software. Re-creating the module using LogiBLOX 2.1i will resolve this problem; please see (Xilinx Answer 4258) for more details.
AR# 6535
日期 07/27/2001
状态 Archive
Type ??????