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AR# 65479

JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim

描述

When running simulation on a single lane transmit configuration example design using QuestaSim, issues have been seen including the simulation timing out on Asserting Sync.

This is due to an issue with QuestaSim optimizing the design during the vopt step.

This Answer Record applies to versions of QuestaSim 10.4b and later.

解决方案

Once QuestaSim has been launched, in the Transcript area enter the following commands to re-optimize the libraries and restart the simulation:

1) For 7 Series use command a, and for UltraScale use b:

a)

vopt +acc -noprotectopt -L unisims_ver -L unimacro_ver -L secureip -L jesd204_v6_2_0 -L xil_defaultlib -L jesd204_phy_v3_0_0 -work xil_defaultlib xil_defaultlib.demo_tb xil_defaultlib.glbl -o demo_tb_opt

b)

vopt +acc -noprotectopt -L unisims_ver -L unimacro_ver -L secureip -L jesd204_v6_2_0 -L xil_defaultlib -L jesd204_phy_v3_0_0 -L gtwizard_ultrascale_v1_6_0 -work xil_defaultlib xil_defaultlib.demo_tb xil_defaultlib.glbl -o demo_tb_opt

2)

restart

3)

run -all

Command a) and b) must be updated to reflect the software version, core version, PHY version, and GT wizard version you are using as follows:

Vivado versionJESD204B core versionJESD204 PHY versionGT Wizard setting (UltraScale)

2015.3 

jesd204_v6_2_0jesd204_phy_v2_0_2gtwizard_ultrascale_v1_6_0
2015.4jesd204_v6_2_1jesd204_phy_v3_0_0gtwizard_ultrascale_v1_6_1
2016.1jesd204_v7_0jesd204_phy_v3_1_0gtwizard_ultrascale_v1_6_2
2016.2jesd204_v7_0_1jesd204_phy_v3_1_1gtwizard_ultrascale_v1_6_3
2016.3jesd204_v7_1jesd204_phy_v3_2_0gtwizard_ultrascale_v1_6_4
2016.4*jesd204_v7_1_1jesd204_phy_v3_2_1gtwizard_ultrascale_v1_6_5
2017.1*jesd204_v7_1_2jesd204_phy_v3_3_0gtwizard_ultrascale_v1_6_6
2017.2*jesd204_v7_1_3jesd204_phy_v3_4_0gtwizard_ultrascale_v1_7_0

 

* For designs in Vivado 2016.4 and later, the XPM library is used for all CDC logic.  

For this reason, the "-L xpm" switch must be added after "-L secureip".

For example, for UltraScale in 2016.4 the following is added:

vopt +acc -noprotectopt -L unisims_ver -L unimacro_ver -L secureip -L xpm -L jesd204_v7_1_1 -L xil_defaultlib -L jesd204_phy_v3_2_1 -L gtwizard_ultrascale_v1_6_5 -work xil_defaultlib xil_defaultlib.demo_tb xil_defaultlib.glbl -o demo_tb_opt

 

An alternative is to add the -noprotectopt switch in the Elaboration tab for Simulation Settings in Vivado:


 


链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
69027 JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim N/A N/A
AR# 65479
日期 07/10/2017
状态 Active
Type 综合文章
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