AR# 65493

描述

Version Found: DDR4 v1.0, DDR3 v1.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

When trying to generate a DDR4/3 configuration requiring more than 3 contiguous banks in a target FPGA that has half banks in between full banks, errors similar to the following are generated:

[#undef] There are certain ports which are still unassigned as per the selected data width 72, design generation can be done correctly once all the bytes/sites are assigned.

Configurations that require more than 3 contiguous banks are:

1. 80-bit interfaces
2. 72-bit, dual slot, dual rank interfaces

An example of a device that would see this error is the xcku095-ffvb2104-3-e which has 5 contiguous banks 65, 66,67,68,69 in the right column with a half bank (68) in between.

解决方案

While this configuration is valid, the DDR4/3 wizard is not counting the half bank as a contiguous bank and therefore failing IP generation.

This issue is planned to be resolved in Vivado 2016.1.

If assistance is needed before this time, please open a Service Request.

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