When I envoke the Xilinx Design Manager (pld_dsgnmgr) or pick the option to envoke the Xilinx Design Manager on my design from Exemplar's P&R tab, for the first time on my design EDIF file I don't get the familiar flow. When I go to Design ->Implement as I used to, I don't get any options, besides picking the version/ revision, and part. As soon as I click on OK the design starts implementing before I have a chance to select my simulation type and effort levels. How do I get to the options as initially it is greyed out?
Due to a change in the Xilinx Design Manager flow a version/revsion must be created before any options can be modified. Upon first starting up pld_dsgnmgr on the design.edif for the first time, you must first do Design -> New Version, then you can do a Design -> Options, to select you simulation type, effort levels etc. If you have partially or completely run implementation then a version/revsion will already exist and the options can be modified, such as after hitting the stop button.