General Description: In the new 2.1i release, the CORE Generator does not directly generate .VHD and .V models for behavioral simulation. (.VEO and .VHO templates are generated instead).
1. The 2.1i CORE Generator does not generate a .VHD or .V file for each core in the 2.1i release. Instead, it creates a .VHO (for VHDL) or .VEO (for Verilog) template file containing the code snippets required to integrate the core into a higher level design block's behavioral simulation netlist.
2. Before any behavioral simulation of a core can be done, you must :
- run the get_models utility to extract the models into a separate source library,
- analyze the library, if required by your simulator, to a library named "xilinxcorelib". (VHDL and compiled Verilog simulators)
- set your simulator to point to the extracted (and analyzed) library