AR# 65652

UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands

描述

Version Found: DDR4 v1.0, DDR3 v1.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

AXI enabled DDR3/DDR4 SDRAM IP designs have the data mask incorrectly tied to GND during Read-Modify-Write commands.

The data mask signals should be driven by the AXI layer of the IP based on the write strobes for Read-Modify-Write (RMW) commands.

解决方案

To fix this issue, the following lines of code inside <ip_name>_ddr3.sv, instance name u_ddr3_mem_intfc:

Go to line 750:

.app_wdf_mask[{APP_MASK_WIDTH{1'b0}}),

replace it with the following:

.app_wdf_mask(c0_ddr3_app_wdf_mask),

Note: Replace "ddr3" with "ddr4" if this is a DDR4 interface.

To prevent Vivado from overwriting the IP edits, it is recommended to create your own IP Repository that contains the RTL edits.

To do this, follow the steps below:

  1. Copy the DDR3/DDR4 SDRAM IP directory, for example: C:\Xilinx\Vivado\2015.3\data\ip\xilinx\ddr3_v1_0
  2. Make your edits to the IP in this copied directory, and save the files anywhere.
  3. Add it in the IP Catalog by clicking IP Settings > Add a Repository, and selecting the saved location of the edited files.

Revision History:

10/12/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 65652
日期 01/17/2018
状态 Active
Type 已知问题
器件
Tools
IP