AR# 65751


UltraScale+ PCI Express Integrated Block - Release Notes and Known Issue


This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express Integrated Block Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools

Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version
(Xilinx Answer 76779)v1.3 (Rev 76779)2021.1
(Xilinx Answer 76337)v1.3 (Rev 76337)2020.2
(Xilinx Answer 75351)v1.3 (Rev 75351)2020.1
(Xilinx Answer 73417)v1.3 (Rev 73417)2019.2
(Xilinx Answer 73071)v1.3 (Rev 73071)2019.2
(Xilinx Answer 72060)v1.3 (Rev 72060)2018.3
(Xilinx Answer 72034)v1.3 (Rev. 72034)2018.3
(Xilinx Answer 71718)v1.3 (Rev. 71718)2018.2
(Xilinx Answer 71191)v1.3 (Rev. 71191)2018.1
(Xilinx Answer 70012)v1.3 (Rev. 70012)2017.3
(Xilinx Answer 69405)v1.2 (Rev.69405)2017.2
(Xilinx Answer 69155)v1.2 (Rev. 69155)2017.1
(Xilinx Answer 68478)v1.1 (Rev. 68478)2016.4
(Xilinx Answer 68310)v1.1 (Rev. 68310)2016.3
(Xilinx Answer 68112)v1.1 (Rev. 68112)2016.3
(Xilinx Answer 68069)v1.1 (Rev. 68069)2016.3
(Xilinx Answer 67712)v1.1(Rev 67712)2016.2
(Xilinx Answer 67617)v1.1 (Rev 67617)2016.2
(Xilinx Answer 67307)v1.1(Rev 67307)2016.1
(Xilinx Answer 67144)v1.1 (Rev 67144)2016.1


Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76779)Tactical Patch for Issue Fixes:
Vivado 2021.1Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 76337)MSI-X Table Size support for more than 8 vectorsVivado 2020.2Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 75351)Tactical Patch for Issue Fixes:
  • Addresses timing issues and critical warnings
v1.3 (Rev7)Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 73417)Tactical Patch for Issue Fixes:
  • CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate with PCIe IP
(Xilinx Answer 73071)Tactical Patch for Issue Fixes:

  • Bug Fix: GT TYPE property passed to IBERT(ISI) IP.
  • Bug Fix: x16 support is added for PCIE_X1Y1 block with GTH_QUAD231 and GTH_QUAD230 for xcku11p-ffve1517 device.
  • Bug Fix: Added Tcl option (disable_user_clock_root) to enable USER_CLOCK_ROOT.
  • Bug Fix: fix for pcie_cq_np_req_count when External MSI-X is use
v1.3 (Rev6)v1.3(Rev7)
(Xilinx Answer 72916)PCIe Integrated Block does not respond correctly to "interrupt_disable" bit setting for Legacy interruptsv1.3 (Rev5)Silicon Issue
(Work-around Provided)
(Xilinx Answer 72690)PCIe core returning Error code 05 for completions received for ATS requestsv1.3 (Rev5)Silicon Issue
(Work-around Provided)
(Xilinx Answer 72060)MSI-X Internal Table access can cause Completion Time-out in Gen3 x16 Configurationv1.3 (Rev1)Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 71877)Reconfigurable Stage-2 support for Tandem PCIe w/ Field Updatesv1.3 (Rev4)Not Resolved Yet
(Xilinx Answer 72034)Allow Gen2 (5.0 GT/s) and 125 MHz AXI Clock Frequency with the xqzu5ev-ffrb900-1M-m devicev1.3 (Rev4)Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 71718)x4 Gen3 Root Port IP generation fails in XAZU5EV-SFVC784-1Q-q devicev1.3 (Rev3)v1.3 (Rev4)
(Xilinx Answer 71191)Link does not train in Gen1 design with Refclk at 125MHz & 250MHz speedsv1.3 (Rev2)v1.3 (Rev3)
(Xilinx Answer 70012)Tactical patch for issue fixes and enhancementsv1.3v1.3(Rev1)
(Xilinx Answer 69405)Tactical patch for issue fixes and enhancementsv1.2(Rev1)v1.3
(Xilinx Answer 69155)Gen3x16 support for -2L devicesv1.2v1.3(Rev1)
(Xilinx Answer 69063)Gen3x16 configuration support on Virtex UltraScale+ -2LV (0.72v) Devicesv1.2v1.3(Rev1)
(Xilinx Answer 68478)x16 Support in xczu7ev (fbv900 and ffvc1156) Devicesv1.1 (Rev2)v1.2(Rev1)
(Xilinx Answer 68310)Link training failure when "System Reset Polarity" is set to "active high"v1.1(Rev2)v1.2(Rev3)
(Xilinx Answer 68112)MSI-X Vector Table and PBAv1.1 (Rev2)v1.1 (Rev3)
(Xilinx Answer 68069)CPLL Calibration Block Integration and MSI-X Core GUI Issuev1.1 (Rev2)v1.2
(Xilinx Answer 67712)Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs:v1.1 (Rev1)v1.1(Rev2)
(Xilinx Answer 67617)X16Gen3 Support for -1L and -2L devicesv1.1 (Rev1)v1.3(Rev1)
(Xilinx Answer 67307)Tactical patch with various fixesv1.1v1.1 (Rev1)
(Xilinx Answer 67307)Various FixesV1.1v1.1 (Rev1)
(Xilinx Answer 67144)Incorrect GT Quad Location for Virtex 9P Devicesv1.1v1.1 (Rev1)


Other Information:

(Xilinx Answer 68134)UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide
(Xilinx Answer 69453)Hot Plug Support
(Xilinx Answer 71446)Link Up Issue with Dell 5810 Systems
(Xilinx Answer 71732)pcie_rq_tag_vld1 behavior in Internal Tag Management mode when straddle option is disabled
(Xilinx Answer 72043)UltraScale+ PCI Express Integrated Block (Vivado 2018.3) - How to enable routing of messages on CQ interface?
(Xilinx Answer 71730)Clock Sharing with sys_clk requirements
(Xilinx Answer 72175)Debug Questions for Link Training Issues
(Xilinx Answer 72471)Integrated Debugging Features and Usage Guide
(Xilinx Answer 71877)Reconfigurable Stage 2 support for Tandem PCIe w/ Field Updates
(Xilinx Answer 76344)Tandem PROM support in Zynq UltraScale+ RFSoC Devices

Revision History:

10/22/2015Initial Release




AR# 65751
日期 08/19/2021
状态 Active
Type 版本说明
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