I am using VCS to simulate the example testbench that comes with the Test Pattern Generator v7.0 and I am receiving the following error:
What does this mean?
How can I resolve it?
This is a known issue in Vivado 2015.3 when simulating the TPG example testbench with VCS simulator and the Vivado project is set for VHDL.
You can work around the error in one of the following ways: