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AR# 6596

2.1i COREGEN, MTI, VERILOG: "WARNING[xx]: .../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when analyzing COREGEN Verilog behavioral models


Keywords: coregen, mti, verilog, analyz, compil, redefinition

Urgency: standard

General Description:
When analyzing/compiling the get_models-extracted COREGEN Verilog behavioral
models, the following warning is issued:

"WARNING[xx]: .../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true."

Similar warnings against the macros named TRUE, false, and FALSE


The simulator's analyzer is complaining that the Verilog macros "true", "TRUE",
"false", and "FALSE" are multply defined in these models. The warning is seen
when several Verilog models which have defined the same macro individually
are analyzed together through the use of wildcards, using the same analyze

The warnings can be ignored since the macro definition in each model
consistently sets the macro of the same name to the same value in all
the models--that is, "TRUE" and "true" are always set to a value of "1",
and "FALSE" and "false" are always set to "0" in all the models that
define them. As a result, the redefinition effectively does not change
the macro value, so it does not adversely affect the functionality of the models.

To avoid these warnings, you may restrict yourself to referencing one model
per analyze command.

AR# 6596
创建日期 05/21/1999
Last Updated 08/01/2001
状态 Archive
Type 综合文章