We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6600

2.1i FPGA Editor - Virtex 1000 has an excessivly long load time


Keywords: long, load, time, V1000, Virtex, FPGA Editor

Urgency: Standard

General Description:
When I invoke FPGA Editor, there is an excessively long load time for large
designs (v1000 for example).

Is there any way to speed up the loading time of the design?


When FPGA Editor takes a long time to load, you can change the inte fpga_editor.ini file to either turn off the stub triming or turn off the routing display.

Follow these steps to accomplish this for a particular design:

1. Open the fpga_editor.ini file (found in $XILINX\data)

2. Go to the bottom of the .ini file in the '#Set what items will be initially displayed' section.

3. Add the line 'setattr main stub-trim off' in the section, or change 'setattr layer routes view on' to 'setattr layer routes view off'.

4. Save the file as "fpga_editor_user.ini" in the
"design\ver\rev" directory.

5. Open the design in Design Manager.

6. Right-click on the design name in the main Design Manager window.

7. Select "Properties".

8. Press the "Revision List..." button.

9. Under the "Filename:" data entry field, find your fpga_editor_user.ini file in the "design\ver\rev" directory.

10. Press the "Set" button, then the "OK" button.

The above steps will allow the fpga_editor_user.ini file to be used only with the appropriate design until changed. The file will be copied from revision to revision, regardless of

This will be fixed in a future release.
AR# 6600
日期 07/09/2001
状态 Archive
Type 综合文章