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AR# 66071

Design Advisory Master Answer Record for Zynq UltraScale+ MPSoC Devices

描述

The Zynq UltraScale+ MPSoC devices are documented in the Zynq data sheet, technical reference manual and other documents.

Important Design Advisories and other considerations that transcend these documents are listed here.

The source point for technical content is the Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

解决方案

Design Advisories Alerted on November 11th, 2019

(Xilinx Answer 72768) Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - 2019.1 FSBL: Image Header Table (IHT) Buffer Overflow [SECURITY]
(Xilinx Answer 72994) Design Advisory for Zynq UltraScale+ MPSoC/RFSoC -  2019.1 XilSKey: PPK Hash buffer overflow [SECURITY]
 
Design Advisories Alerted on August 12th, 2019
 
(Xilinx Answer 72572) Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: 2019.1 XilSKeyPUF Registration is incorrect [SECURITY]
(Xilinx Answer 72588) Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Encrypt Only Boot Mode Unauthenticated Boot and Partition Headers [SECURITY]

 

Design Advisories Alerted on April 22nd, 2019

(Xilinx Answer 71952) Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: A glitch might be observed on the PMU GPO1[2] (MIO34) following assertion of PS_POR_B

 

Design Advisories Alerted on August 6th, 2018

(Xilinx Answer 71293)   Design Advisory for Zynq UltraScale+ MPSoC: 2017.x FSBL performs the security operations on the partitions based on the content of the partition headers. [SECURITY]
(Xilinx Answer 71326)   Design Advisory for Zynq UltraScale+ MPSoC: 2017.x, 2018.1, 2018.2 FSBL is not checking all of the RSA_EN eFUSEs [SECURITY]

 

Design Advisories Alerted on March 19th, 2018

(Xilinx Answer 70622) Design Advisory for Zynq UltraScale+ MPSoC: 2017.x Xilinx Development tools and software re-use the same AES Key and IV pair across multiple partitions. [SECURITY]

 

Design Advisories Alerted on April 17th, 2017

(Xilinx Answer 69034) Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards
(Xilinx Answer 68615) Design Advisory for Zynq UltraScale+ MPSoC: Boot from NAND might fail if there is data corruption in the first parameter page

Design Advisories Alerted on April 10th, 2017

(Xilinx Answer 68832) Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier) [SECURITY]

Design Advisory Alerted on December 5th, 2016

(Xilinx Answer 68210) FSBL authenticates the boot image in external DDR [SECURITY]

Design Advisory Alerted on October 17th, 2016

(Xilinx Answer 67861) How do I upgrade from Vivado 2016.2 and earlier versions?

 

Design Advisory Alerted on April 18th, 2016

(Xilinx Answer 66944) Design Advisory for Zynq UltraScale+ MPSoC and Kintex UltraScale+ FPGA - Updated Package Pinouts

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A

子答复记录

AR# 66071
日期 11/08/2019
状态 Active
Type 设计咨询
器件
的页面