AR# 66171


Zynq-7000 SoC ZC706 Evaluation Kit - Rev 2.0 - POR calculation in schematic is not accurate


The reset circuitry for the processing system of the ZC706 is described on page 15 of the ZC706 rev 2.0 schematics.

This shows C6 as a 5600 pF capacitor, and includes a note that the POR delay is 13.2 ms. Is this correct?



On the ZC706 Rev 2.0, C6 does have the value 5600 pF (this can be confirmed in the Build of Materials for that revision of the kit).

The C6 POR delay calculation, however uses the value 3300 pF. 

This is incorrect. The correct calculation, using the C6 = 5600 pF is:

C6 = 5600pF, POR delay = 22.4 ms



Answer Number 问答标题 问题版本 已解决问题的版本
51899 Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 66171
日期 06/13/2018
状态 Active
Type 综合文章
Boards & Kits
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