AR# 66181


MIG 7 Series DDR3 - IBUF_LOW_PWR may be incorrectly enabled in Vivado 2015.1 and 2015.2


Version Found: MIG 7 Series v2.3 Rev1

Version Resolved: See (Xilinx Answer 54025)

There is an issue with the Vivado Synthesis tool where the IBUF_LOW_PWR setting is incorrectly turned "ON" for the DQS and DQ pins, even though this attribute is set to "OFF" in the MIG RTL for all configurations.
This incorrect setting can result in intermittent calibration failures.
The calibration failures are observed during the OCLKDELAYED stage, and the failure mechanism is that reads are being randomly dropped.
The correct read data is being returned to the FPGA, and SI and alignment on DQ/DQS looks correct when probed on the board, however the data is not getting latched into the IN_FIFO.

Note: the IBUF_LOW_PWR option is not controlled by the "I/O Power Reduction" feature in the GUI, and should be set to "OFF" for all configurations.


This Synthesis issue is resolved in Vivado 2015.3.

If you are seeing calibration failures with MIG designs built in 2015.1 or 2015.2, please upgrade your design to at least Vivado 2015.3.

If upgrading is not possible, the IBUF_LOW_PWR option can be manually set to "OFF" in the top level .xdc file:

set_property IBUF_LOW_PWR FALSE [get_ports {ddr3_dqs_p[*]}]
set_property IBUF_LOW_PWR FALSE [get_ports {ddr3_dqs_n[*]}]
set_property IBUF_LOW_PWR FALSE [get_ports {ddr3_dq[*]}]

Revision History:

12/10/2015 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 66181
日期 12/21/2015
状态 Active
Type 已知问题
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