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AR# 66183

Zynq UltraScale+ MPSoC 处理系统 IP - 发布说明和已知问题


此答复记录包含 Zynq UltraScale+ MPSoC 处理系统 IP 的发布说明和已知问题,包括以下内容:

  • 通用信息
  • 已知和已解决的问题
  • 修订历史

Zynq UltraScale+ MPSoC 处理系统 IP 页面:





如欲查看新特性列表和所有版本添加的器件支持,请参见 Vivado 设计工具中提供该核的 Change Log 文件。


此表将内核版本关联至首个包含该表的 Vivado 设计工具发布版本。

内核版本Vivado 工具版本
初始版本 2015.2
1.0 (Rev 1)2015.3
1.0 (Rev 2)2015.4


表提供的答复记录可用于使用 Zynq UltraScale+ MPSoC IP 的通用指南。

(Xilinx Answer 55248)Vivado 时序和 IP 约束
(Xilinx Answer 65467)cZynq UltraScale+ MPSoC - 启动与配置
(Xilinx Answer 64375)Xilinx UltraScale+ MPSoC 解决方案中心
Zynq UltraScale+ MPSoC — 芯片版本差异
(Xilinx Answer 66071)面向 Zynq UltraScale+ MPSoC 器件的设计咨询


下表是 Zynq UltraScale+ MPSoC 的已知问题,从最初在 Vivado 2015.4 工具中发布的 v1.0 (Rev 2) 开始。


(Xilinx Answer 67861)Zynq UltraScale+ MPSoC 处理系统的设计咨询 — 如何升级 Vivado 2016.2 及更早的版本?
(Xilinx Answer 68184)
PS LPDDR4 设备没有完成 psu_init 初始化 2016.32016.4
(Xilinx Answer 65982)Zynq UltraScale+ MPSoC、Vivado 2015.4 — 支持 PS DDR3/DDR4/LPDDR4 和 GTR 收发器的的补丁2015.42016.1
(Xilinx Answer 66218)Zynq UltraScale+ MPSoC — 由于 psu_int.c 和 psu_init.tcl 之间的差异, psu_init 流不起作用2015.42016.1
(Xilinx Answer 66219)Zynq UltraScale+ MPSoC — 通过在 JTAG 模式下配置处理器模块级软件控制的复位寄存器,使处理器脱离复位状态2015.42016.1
(Xilinx Answer 66295)Zynq UltraScale+ MPSoC — PS-PL AXI 接口在 64 位或 32 位位宽时不能正常工作(M_AXI_HP0_LPD 是 128 位)2015.42016.3
(Xilinx Answer 66220)Zynq UltraScale+ MPSoC — 为 PS+PL 设计复位信号的可用性2015.42016.1
(Xilinx Answer 66223)Zynq UltraScale+ MPSoC — 支持 DDR 默认配置的 DRC2015.42016.1
(Xilinx Answer 66224)Zynq UltraScale+ MPSoC — 项目设置为 VHDL(主要针对 PS 专用设计)时,Zynq UltraScale+ MPSoC 封装程序弹出语法错误2015.42016.1
(Xilinx Answer 66225)Zynq UltraScale+ MPSoC — 当我们在内存中创建了可以从特定主机访问的片段时,会出现移交给软件 (SDK) 的限制2015.42016.1
(Xilinx Answer 66226)Zynq UltraScale+ MPSoC — 将 PS DDR 作为代码执行内存为 MicroBlaze 创建应用时发生故障2015.42016.1
(Xilinx Answer 66227)Zynq UltraScale+ MPSoC — 使用支持从接口的分裂时钟2015.42016.1
(Xilinx Answer 66247)Zynq UltraScale+ MPSoC — 在 Windows 和 Linux 主机之间报告的 PS 电源数略有不同2015.42016.1
(Xilinx Answer 66045)Zynq UltraScale+ MPSoC — 使用 MIO 时,如何将 UART MODEM 信号连接至 EMIO?2015.42016.1
(Xilinx Answer 66571)Zynq UltraScale+ MPSoC — PS DDR 拓扑的处理器系统 IP GUI 限制2015.42016.1


12/12/2015 - 初始版本



Answer Number 问答标题 问题版本 已解决问题的版本
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
63538 Vivado Design Suite 2015 - Known Issues N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
55248 Vivado Timing and IP Constraints - Why do I get the following CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks, for my IP, or why do I get CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay? N/A N/A
65467 Zynq UltraScale+ MPSoC - Boot and Configuration N/A N/A
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
66071 Design Advisory Master Answer Record for Zynq UltraScale+ MPSoC Devices N/A N/A
66218 Zynq UltraScale+ MPSoC Processing System IP - psu_init flow is not working due to differences between psu_int.c and psu_init.tcl N/A N/A
66219 Zynq Ultrascale+ MPSoC Processing System IP - Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode N/A N/A
66220 Zynq UltraScale+ MPSoC Processing System IP - Reset Signal Availability for PS+PL designs N/A N/A
66224 Zynq UltraScale+ MPSoC Processing System IP - Zynq UltraScale+ MPSoC wrapper throws syntax error when project is set to VHDL - for PS-only design N/A N/A
66225 Zynq UltraScale+ MPSoC SDK - Limitations with hand-off to software (SDK) when we have segments created in memory to be accessible from a specific master. N/A N/A
66226 Zynq UltraScale+ MPSoC, SDK - Failure when creating an application for MicroBlaze with PS DDR as code execution memory N/A N/A
66227 Zynq UltraScale+ MPSoC Processing System IP - Use of Split clock with slave interface N/A N/A
65982 Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support N/A N/A
66247 Zynq Ultrascale+ MPSoC Processing System IP - Slightly different PS power numbers reported between Windows and Linux hosts N/A N/A
66295 Zynq UltraScale+ MPSoC Processing System IP - PS-PL AXI Interfaces do not function correctly at 64-bit or 32-bit widths (or 128-bits for M_AXI_HP0_LPD) N/A N/A
66223 Zynq UltraScale+ MPSoC Processing System IP - Incorrect DRC with default configuration for DDR N/A N/A
66045 Zynq UltraScale+ MPSoC, Vivado 2015.4: How do I connect the UART MODEM signal to EMIO while using MIO? N/A N/A
66571 Zynq UltraScale+ MPSoC, Vivado 2015.4 - Processor System IP GUI Limitations with PS DDR topologies N/A N/A
68184 Zynq UltraScale+ MPSoC - PS LPDDR4 devices do not complete psu_init initialization N/A N/A
AR# 66183
日期 10/22/2019
状态 Active
Type 版本说明
Tools More Less