Version Found: MIG 7 Series v2.4
Version Resolved: See (Xilinx Answer 54025)
When using the MIG 7 Series IP core, there are internal Debug Signals available that can be used for debugging purposes.
To generate these signals as top-level I/O ports, there is an option in the MIG IP GUI to enable/disable them.
This option is not available when using MIG 7 Series in IP Integrator.
However, these debug signals still exist internally in the MIG IP RTL. If the debug signals are required when using IP Integrator, the ILA insertion flow can be used to insert ILAs on the debug ports using the synthesized DCP netlist.
Revision History:
01/18/2016 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54025 | MIG 7 Series - IP Release Notes and Known Issues for Vivado | N/A | N/A |
| AR# 66422 | |
|---|---|
| 日期 | 01/21/2016 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |