Version Found: DDR4 v1.1
Version Resolved: See (Xilinx Answer 69035)
The DDR4 IP incorrectly programs the WR value for Mode Register 0 (MR0) for some scenarios. For example, for DDR4 operation at 2400Mb/s tWR=15ns and tCK=833ps so the Write Recovery (WR) time should be 18 clocks.
However, the DDR4 IP incorrectly configured MR0 for 20 clocks which can have a negative impact on controller efficiency or result in DRAM errors when using the PHY Only IP.
For example, the following error message might be seen during PHY Only simulations if the users controller is programmed for 18 clocks but the PHY IP is programmed for 20:
To fix the issue you can simply change the MR0 parameter value inside the <core_name>_ddr4.sv file (for full IP) and/or inside <core_name>_phy_ddr4.sv (PHY Only IP):
Note: Make sure that Out Of Context is disabled for the IP. Otherwise, you risk any RTL change you make being overwritten by Vivado during synthesis.
Alternatively, you can create an IP Repository for the DDR4 IP, and hard code the MR0 parameter value to 18CK.
This would enable you to use Out of Context and will ensure your RTL changes never get overwritten.
To use the IP Repository flow, follow these steps:
1) Copy the DDR4 Controller directory from your Vivado install area.
2) Make your edits to the source code in this copied directory and store the files in a location of your choice, preferably somewhere in your project directory.
3) You will then need to add it in the IP Catalog.
Click on the IP Settings:
4) Then Add a Repository, point to the newly edited PHY directory and Refresh All. The IPs should be shown in the repository in the lower box:
The screen capture below shows an example of what it should look like.
The IP in the standard MIG directory will now be over-ridden and you will see your edits when you generate the IP and look at the relevant code.
01/25/2016 - Initial Release
12/18/2019 - Updated title to indicate UltraScale/UltraScale+