AR# 6655


FPGA Express - How do I do operator overloading in FPGA Express?


General Description:

If I have two packages that have the same operator, how do I

chose which package the operator comes from? For example, the

Synopsys packages std_logic_signed and std_logic_unsiged both

have the "=" defined. If both packages are needed in the design,

which operator gets chosen?


To reolve this, the operator has to be declared as:


So in some VHDL code, the function would look like:

result <= IEEE.std_logic_unsigned."="(in1,"0000");
AR# 6655
日期 03/22/2011
状态 Archive
Type 综合文章
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