AR# 66560

UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component

描述

Version Found: DDR3 and DDR 4 v1.1

Version Resolved: See (Xilinx Answer 69035) for DDR4 and see (Xilinx Answer 69036) for DDR3

When I try to generate a DDR4/3 configuration requiring a twin die component, errors similar to the following are generated:

[Mig 66-116] Custom Part (DDR3_CUSTOM) with parameter: CA Mirror having value: 0 is invalid

When I edit the .csv file to set CA Mirror to 1, the following error is displayed:

[Mig 66-116] Custom Part (DDR3_CUSTOM) with parameter: CA Mirror having value: 1 is invalid

解决方案

CA_MIRROR is a DDR4/3 parameter that is set to "ON" for DIMMs that support address mirroring. Twin die parts do not use address mirroring. 

Therefore, the error message generated is not valid, and will be fixed in the 2016.1 release.

When targeting a twin die part in versions prior to 2016.1, either select one of the available default twin die parts, or if targeting a 64-bit data width, specify a SODIMM in the custom part .csv file with CA_MIRROR set to 0.

Revision History:

09/18/2017 - Linked to master DDR3 and DDR4 ARs

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 66560
日期 01/16/2018
状态 Active
Type 已知问题
器件 More Less
IP