AR# 66565


LogiCORE DisplayPort v6.1 (Rev. 1) - Why is the lnk_fwdclk_p/n reference input clock grounded for the RX IP for UltraScale Devices?


UltraScale devices require two clock sources for the DisplayPort RX IP. The first clock lnk_fwdclk_p is for the line rates 2.7 and 5.4, and this comes as a forwarded clock from the DP159 re-timer.

Because the forwarded clock frequency from DP159 for 1.62MHz line rate falls under the CPLL holes for the UltraScale devices, we need to provide a separate input clock of 270MHz.

Hence there are two reference clocks for the Display Port IP connected in the DP core as below
  • MGTREFCLK0 - lnk_clk_p/n - external fixed clock of 270MHz
  • MGTREFCLK1 - lnk_fwdclk_p/n - forwarded clock coming from the DP159

When I generate the DisplayPort RX core for any UltraScale Device and try to trace the lnk_fwd_clk connectivity to the MGTREFCLK1, it is connected to ground. 

What is the reason for this and how can I fix this?


This is a known issue in the Vivado 2015.4 DisplayPort v6.1 (Rev. 1) GUI.

This issue is resolved in Vivado 2016.1.

Please see (Xilinx Answer 66301) for a patch for the DisplayPort v6.1 (Rev. 1) in Vivado 2015.4.




AR# 66565
日期 04/01/2016
状态 Archive
Type 综合文章
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