AR# 66571


Zynq UltraScale+ MPSoC, Vivado 2015.4 - Processor System IP GUI Limitations with PS DDR topologies


This article lists the current open PS DDR limitations with the configuration GUI in Vivado 2015.4.



1. As per the Zynq UltraScale+ Technical Reference Manual, 32-bit + ECC is supported:


On Page 271 it states:

"Error correction code (ECC) support in 32-bit and 64-bit mode, 2-bit error detection and 1-bit error correction."

However, in the IP GUI, it shows as Disabled without any drop-down option for 32-bit.


2. For DDR4 with an Effective DRAM Bus Width of 64-bit, the DRAM IC Bus Width can only go up to 32 bits.

3. 16-bit DDR support does not exist in the Zynq UltraScale+ controller and needs to be removed from the GUI.

These issues are planned to be fixed starting in Vivado 2016.1.



Answer Number 问答标题 问题版本 已解决问题的版本
66194 Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller N/A N/A
66183 Zynq UltraScale+ MPSoC 处理系统 IP - 发布说明和已知问题 N/A N/A
AR# 66571
日期 02/11/2016
状态 Active
Type 已知问题
People Also Viewed