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AR# 6676

JTAG - How do I instantiate the BSCAN symbol to enable JTAG use in XC4000 and Spartan devices using HDL?

Description

Keywords: JTAG, pin, TMS, instantiate, VHDL, FPGA Express

Urgency: Standard

General Description:
I am using VHDL to access the JTAG capabilities of the XC4000/Spartan families. How do I instantiate the BSCAN symbol to enable JTAG use in XC4000 and Spartan devices using HDL?

解决方案

The following VHDL example illustrates the instantiation of the BSCAN Macro in Xilinx devices. (This code should be used only for reference.)

entity example is
port (a, b: in STD_ULOGIC; c: out STD_ULOGIC);
end example;

architecture xilinx of example is

component BSCAN
port(
TDO : out STD_ULOGIC ;
DRCK : out STD_ULOGIC ;
IDLE : out STD_ULOGIC ;
SEL1 : out STD_ULOGIC ;
SEL2 : out STD_ULOGIC ;
TDI : in STD_ULOGIC ;
TMS : in STD_ULOGIC ;
TCK : in STD_ULOGIC ;
TDO1 : in STD_ULOGIC ;
TDO2 : in STD_ULOGIC );
end component;

component TCK
port(
I : inout STD_ULOGIC);
end component;


component TDI
port(
I : inout STD_ULOGIC);
end component;

component TMS
port(
I : inout STD_ULOGIC);
end component;

component TDO
port(
O : in STD_ULOGIC);
end component;


signal tck_net : STD_ULOGIC;
signal tdi_net : STD_ULOGIC;
signal tms_net : STD_ULOGIC;
signal tdo_net : STD_ULOGIC;

begin

u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net);
u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);

process(b)
begin
if (b'event and b='1') then
c <= a;
end if;
end process;

end xilinx;
AR# 6676
创建日期 09/01/2007
Last Updated 08/25/2003
状态 Archive
Type ??????