AR# 66786


UltraScale+/ Zynq UltraScale+ MPSoC SelectIO: Interfacing LVDS signals with 1.2V I/O banks


In many cases there is a need to connect LVDS drivers to banks powered at 1.2V. For instance the system clock for the memory controller is from an LVDS oscillator that can be powered at 1.8V or above.

How can this be accommodated in a 1.2V I/O bank?



LVDS inputs can be placed in banks with VCCO levels that are different to the required level for outputs.


Some important criteria to consider:


  1. The optional internal differential termination cannot be used (DIFF_TERM_ADV = TERM_NONE or DIFF_TERM = FALSE (default value) ), unless the VCCO voltage is at the level required for outputs.
  2. The differential signals at the input pins must meet the VIN requirements in the Recommended Operating Conditions table of the device data sheet.
  3. The differential signals at the input pins must meet the VIDIFF and VICM requirements in the DC Specifications tables in the device data sheet.


If the LVDS driver has a wider swing and common mode such that 2 and 3 above cannot be met, it will be necessary to provide an external circuit to both AC-couple and DC-bias the pins.


Another option to consider is using DIFF_SSTL12.

In Pseudo-Differential I/O standards, the receiver is the same buffer that is used for true differential I/O standards such as LVDS in the UltraScale+ HP bank.

You are still required to meet the VIN specification in the data sheet and you still need to satisfy the VICM requirement for DIFF_SSTL12.

To do this it might be necessary to use AC coupling.


Because you have DIFF_SSTL12 then you will be able to terminate with the on-die termination options for this I/O standard.

If you need AC coupling you will be able to use the DQS_BIAS = TRUE option for the I/O. This will eliminate the need for a biasing network on the board.



AR# 66786
日期 03/25/2016
状态 Active
Type 综合文章
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