AR# 6687

3.1i XST - ERROR: (VLG__5002). top.v Line xx. Component 'component_name' is not in up, down, or top-level path

描述

Keywords: XST, Verilog, hierarchy, name, VLG__5002

Urgency: Standard

General Description:
The following error is reported:

ERROR: (VLG__5002). top.v Line xx. Component 'component_name' is not in up, down, or top-level path

if you are referencing signals in a hierarchical manner, such as:

assign top.component_name.signal_name=4'd9;

解决方案

This problem is fixed in the latest 3.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 3.1i Service Pack 3.
AR# 6687
日期 08/20/2002
状态 Archive
Type 综合文章