AR# 66938

UltraScale+ DDR4 - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation

描述

Version Found: DDR4 v2.0

Version Resolved: See (Xilinx Answer 69035)

When targeting DDP (Dual Die Package/Twin Die) DDR4 components in UltraScale+, the data width can be expanded with multiple components. 

For the DDR4 DDP components at -3 and -2 (VCCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP devices. 

For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (VCCINT = 0.85V) speed grades.

As a result of the double loading inside the DDP part and Xilinx signal integrity analysis, in order to achieve 2400Mbps, the number of components needs to be limited to five. 

For six or more components the frequency must be limited to 2133Mbps.

解决方案

In Vivado 2016.1, this frequency and component number limit is not adhered to within the DDR4 Wizard.

In addition, if an older IP version that violates the frequency requirement is brought into a newer version of Vivado, no DRC errors will occur.

You will need to manually ensure when selecting six or more components to set the frequency to 2133Mbps or less.

Please check the latest datasheets for accurate derating information:

  • (DS892) Kintex UltraScale
  • (DS922) Kintex UltraScale+
  • (DS893) Virtex UltraScale
  • (DS923) Virtex UltraScale+
  • (DS925) Zynq UltraScale+ MPSoC

 

Revision History:

04/13/2016 Initial Release
08/11/2016 Updated to include message on DRC
06/13/2018 Updated to point to DS and include updated DS language
10/03/2018 Fixed a typo in the description to say "use single rank component" instead of "use single rank DIMM" for the 5 or less components scenario

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 66938
日期 09/17/2020
状态 Active
Type 已知问题
器件
Tools
IP