AR# 67023


MIG 7 Series RLDRAM3 - Write Calibration failures can occur when Read Latency (RL) is larger than 12


Version Found: v2.3

Version Resolved: (Xilinx Answer 45195)

Write Calibration failures can occur across temperature variation when the Read Latency (RL) is larger than 12. There is an internal parameter called START_WAIT_TIME that controls when Bitslip checks for valid read data.

START_WAIT_TIME is set to 12 by default. However, if the Read Latency parameter RD_LATENCY is set to 12 or higher, there is a possibility that the read Bitslip logic will detect invalid data for the first clock cycle (when it is actually the 3-stated data) then will receive valid data on the next clock cycle.

When calibration first detects bad data, it is due to Bitslip reading the data when it should not be. This results in write calibration errors in hardware.


To resolve this issue, increase the START_WAIT_TIME parameter value in the mig_7series_v3_0_qdr_rld_phy_read_stage2_cal.v file to RD_LATENCY+3.

For example, if the RD_LATENCY is 12 then the START_WAIT_TIME should be changed to:

localparam START_WAIT_TIME = (nCK_PER_CLK == 2) ? 3 : 15;

For instructions on modifying IP RTL, refer to (Xilinx Answer 57546).

Revision History:

06/06/2016 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 67023
日期 07/13/2016
状态 Active
Type 已知问题
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