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AR# 67029

Using a transceiver reference clock as system clock for a debug core such as IBERT

描述

The system clock for a debug core needs to be free running. This must be true for the initial startup as well, in order to detect the debug core properly.

The reference clock input for transceivers can be used as a clock source to drive a fabric clock (see the relevant transceiver and clocking resources user guide for conditions) and it is usually a free running clock. 

However, the internal reference clock signal can have an initial unstable phase while the input termination is settling during/after configuration.

See (Xilinx Answer 65199) For 7 Series examples. The time needed for this phase depends on the external AC coupling and input signal parameters.

解决方案

To ensure that the refclk input can be used as system clock for a debug core, measure the startup of the internal clock signal under the application conditions.

If it is present right away (free running), there should be no problem with using it.

 

All reference clock inputs can be used that are available in the device.

The IBERT wizard only gives the reference clock inputs as a choice for the system clock. These are previously selected in the 'Protocol Selection' tab. 

If another reference clock input needs to be used, the necessary changes need to be made manually in the IBERT example design. 

The following would need to be done:

Generate the IBERT example design and select an external clock source with the frequency available at the later used reference clock input.

In the example design top-level module:

  • Increase the refclk port width if necessary and instantiate additional IBUFDS_GTE*
  • For 7 Series, connect the O output of this IBUFDS_GTE2 to the SYSCLK_I input of the IBERT core
  • for UltraScale/UltraScale+, connect the ODIV2 output of the IBUFDS_GTE* to the input of a BUFG_GT instance and connect its output to the 'clk' input of the IBERT core

In the example design .xdc file:

  • Assign correct pin locations for the new reference clock input
  • Adjust the create_clock command for D_CLK to the new used reference clock port
AR# 67029
日期 09/11/2017
状态 Active
Type 综合文章
IP
  • Virtual Input/Output (VIO)
  • IBERT for 7 Series GTH Transceivers
  • IBERT for 7 Series GTP Transceivers
  • More
  • IBERT for 7 Series GTX Transceivers
  • IBERT UltraScale GTY
  • Integrated Logic Analyzer
  • JTAG to AXI Master
  • Less
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