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AR# 67043

JESD204 v6.1, v6.2, v7.0 and JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - Defaults to DFE Equalisation mode

描述

When using the JESD204 v6.1., v6.2, or v7.0 core and/or the JESD204 PHY v2.0, v3.0, v3.1 core, the value of RXLPMEN (LPM Mode Enable) is set to 0 by default.

This results in the default equalization mode being set to DFE rather than LPM. This is unlikely to be suitable in the majority of applications.

It is recommended that the equalization mode be changed to LPM unless the use of DFE has been discussed with Xilinx or you fully understand the implications of using DFE.

解决方案

This issue is seen with RXLPMEN in all circumstances.

There are five different solutions, depending on how the JESD204 core is generated.

The first two cases occur when the JESD204 core is generated with "Include Shared Logic in core" option selected.


Case 1: The "Additional transceiver control and status ports" option is enabled:

This setup exposes the RXLPMEN port but it is not wired up to anything and it defaults to the incorrect value. This is resolved at the top level, where the JESD core is instantiated.

Tie the RXLPMEN port to the correct value of 1'b1.


Case 2: The "Additional transceiver control and status ports" option is not enabled:

This setup does not expose the RXLPMEN port. This ties RXLPMEN internally to the incorrect value. This is resolved by enabling the "Additional transceiver control and status ports" option and following the solution to case 1 above.

The remaining cases occur when the JESD204 core generated with the "Include Shared logic in example design" option selected and therefore uses the separate JESD204 PHY core.


Case 3: The JESD204 PHY core is generated with the "AXI-Lite Management Interface" option enabled. The "Additional transceiver control and status ports" option is irrelevant in this case.

This setup exposes the RXLPMEN port to a register that is accessible via the AXI-Lite interface. This register defaults to the incorrect value. This is resolved by writing 0x1 to register 0x608 (RXLPMEN) then writing 0x1 followed by 0x0 to register 0x60C (DFELPMRESET) using the AXI-Lite interface on the JESD204 PHY.


Case 4: The JESD204 PHY core is generated with the "AXI-Lite Management Interface" option not enabled and the "Additional transceiver control and status ports" option enabled.

This setup exposes the RXLPMEN port but it is not wired up to anything and it defaults to the incorrect value. This is resolved at the top level, where the JESD PHY is instantiated.

Tie the RXLPMEN port to the correct value of 1'b1.


Case 5: The JESD204 PHY core is generated with the "AXI-Lite Management Interface" option not enabled and the "Additional transceiver control and status ports" option not enabled.

This setup does not expose the RXLPMEN port. This ties RXLPMEN internally to the incorrect value. 

This is resolved by either enabling the "AXI-Lite Management Interface" option or the "Additional transceiver control and status ports" option and following the solution to case 3 or 4 above.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
61911 LogiCORE IP JESD204 PHY 核 - 发布说明与已知问题 N/A N/A
AR# 67043
日期 05/27/2016
状态 Active
Type 综合文章
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