Version Found: DDR4 v2.0
Version Resolved: See (Xilinx Answer 69035)
Targeting the following list of DDR4 RDIMMs and LRDIMMs in Vivado 2016.2 and earlier generates two sets of CK/CK# clock pairs.
However, their data sheets show that the CK pair is terminated but not used.
You can leave the extra CK/CK# clock pair connected to the RDIMM as it is terminated but not used.
Starting in Vivado 2016.2, the DDR4 IP will generate only 1 CK/CK# for the DDR4 3DS RDIMM part M393A8K40B21-CTC
Starting in Vivado 2016.3, the DDR4 IP will generate only 1 CK/CK# for the rest of the DDR4 (L)RDIMMS: MTA18ASF2G72PDZ-2G3, MTA36ASF4G72PZ-2G3. MTA36ASF4G72LZ-2G3, MTA36ASF2G72LZ-2G1, MTA72ASS4G72LZ-2G3, and MTA72ASS4G72LZ-2G1
The following CRITICAL WARNING message will be seen:
The following message is displayed in the ip_upgrade.log file:
These messages are safe to ignore. Update the top level wrapper and XDC to match the port width change.
04/18/2016 - Initial Release
07/05/2016 - Revised to include more parts for Vivado 2016.3