AR# 67054

UltraScale/UltraScale+ DDR4 - Extra CK/CK# clock pair generated for some RDIMMs and LRDIMMs


Version Found: DDR4 v2.0

Version Resolved: See (Xilinx Answer 69035)

Targeting the following list of DDR4 RDIMMs and LRDIMMs in Vivado 2016.2 and earlier generates two sets of CK/CK# clock pairs. 

However, their data sheets show that the CK[1] pair is terminated but not used.


  • MTA18ASF2G72PDZ-2G3
  • MTA36ASF4G72PZ-2G3
  • M393A8K40B21-CTC


  • MTA36ASF4G72LZ-2G3
  • MTA36ASF2G72LZ-2G1
  • MTA72ASS4G72LZ-2G3
  • MTA72ASS4G72LZ-2G1


You can leave the extra CK/CK# clock pair connected to the RDIMM as it is terminated but not used.

Starting in Vivado 2016.2, the DDR4 IP will generate only 1 CK/CK# for the DDR4 3DS RDIMM part M393A8K40B21-CTC

Starting in Vivado 2016.3, the DDR4 IP will generate only 1 CK/CK# for the rest of the DDR4 (L)RDIMMS: MTA18ASF2G72PDZ-2G3, MTA36ASF4G72PZ-2G3. MTA36ASF4G72LZ-2G3, MTA36ASF2G72LZ-2G1, MTA72ASS4G72LZ-2G3, and MTA72ASS4G72LZ-2G1

The following CRITICAL WARNING message will be seen:

Coretcl 2-1279] The upgrade of 'IP ddr4_0' has identified issues that may require user intervention. Please review the upgrade log 'ip_upgrade.log', and verify that the upgraded IP is correctly configured.

The following message is displayed in the ip_upgrade.log file:

3. Connection Warnings
Detected external port differences while upgrading 'ddr4_0'. These changes may impact your design.
-Upgraded port 'c0_ddr4_ck_c' width 1 differs from original width 2
-Upgraded port 'c0_ddr4_ck_t' width 1 differs from original width 2

These messages are safe to ignore. Update the top level wrapper and XDC to match the port width change.

Revision History:

04/18/2016 - Initial Release

07/05/2016 - Revised to include more parts for Vivado 2016.3



Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67054
日期 01/17/2018
状态 Active
Type 已知问题
器件 More Less