A new DRC check has been added in Vivado 2016.1 that enforces a limit of six global clocks per half I/O bank, as that is the number of clock spines available.
However, a case has been seen where a false positive was flagged related to BUFG_GT clocks.
If an existing design had routed successfully in previous revisions but fails in Vivado 2016.1, then one of two possibilities is occurring:
The difference between these two conditions can be determined by examining the timing of the clock nets driven by the clock buffers listed in the error message and/or checking the placement of the loads of those nets to see if they actually have loads in the I/O column of the bank in question.
The false DRC checks can be disabled by setting the following parameters before running implementation:
set_param place.enablePrePlaceDrcChecks false
set_param route.noDrc true
Note: Disabling DRC for placement and routing is something that should only be done when necessary. Any real errors will still be caught at bit file generation, but would be caught sooner with DRC enabled.
The false DRC errors are scheduled to be fixed for Vivado 2016.2.