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AR# 67111

UltraScale Integrated Block for PCI Express, Virtex-7 Gen3 Integrated Block for PCI Express, and DMA Subsystem for PCI Express (Vivado 2016.1) - Issue with Legacy Interrupt Mode

描述

Version Found: 2.0

Version Resolved and other Known Issues: (Xilinx Answer 65443)

The patch provided with this answer record fixes the following issues with the Virtex-7 Gen3 Integrated Block for PCI Express, UltraScale Integrated Block for PCI Express, and the DMA Subsystem for PCI Express core in Vivado 2016.1.

  • There should be two acks from the core for every user interrupt: one for assertion and one for de-assertion. The second ack for de-assertion is missing.

    This article is part of the PCI Express Solution Centre

    (Xilinx Answer 34536)Xilinx Solution Center for PCI Express

    解决方案

    [Note: It is required to install the respective patches when using the Virtex-7 FPGA Gen3 Integrated Block for PCI Express and UltraScale Gen3 Integrated Block for PCI Express cores standalone.]


    This is a known issue to be fixed in a future release of the core. To resolve the issue, please install the patches attached to this answer record as described below.

    • The provided patches are for Vivado 2016.1 for the DMA Subsystem for PCI Express, Virtex-7 FPGA Gen3 Integrated Block for PCI Express, and UltraScale Gen3 Integrated Block for PCI Express cores.
    • The patch for DMA Subsystem for PCI Express is required to be installed for both Virtex-7 FPGA and UltraScale devices. The other patches need to be installed based on the selected device.

    • Unzip the attached zip files to the directory of your choice.
    • Open Vivado 2016.1 and create a new project.
    • Open IP catalog. Right click the core you are using and choose IP Settings.
    • Click Add Repositories and point it to the location where you have unzipped the patch.
    • Click OK and you are now ready to generate the core.
    • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
    • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

    Note: "Version Found" refers to the version where the problem was first discovered.

    The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

    Revision History

    06/06/2016 - Initial release

    06/03/2018 - Removed information on fix regarding left shift of the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters. See (Xilinx Answer 71169).

     

    附件

    AR# 67111
    日期 06/06/2018
    状态 Active
    Type 已知问题
    IP
    • DMA for PCI Express (PCIe) Subsystem
    • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
    • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
    的页面