Version Found: 2.0
Version Resolved and other Known Issues: (Xilinx Answer 65443)
The following issues have been seen with the Virtex-7 Gen3 Integrated Block for PCI Express, UltraScale Integrated Block for PCI Express, and the DMA Subsystem for PCI Express core in Vivado 2016.1.
The patch consists of logic to fix an issue in the core where the core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters for PF0,PF1, VF0-VF5 by 3 bits.
The fix right shifts the values by 3 bits so that the implemented value in hardware is the same as the one programmed during the core configuration.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
[Note: It is required to install the respective patches when using the Virtex-7 FPGA Gen3 Integrated Block for PCI Express and UltraScale Gen3 Integrated Block for PCI Express cores standalone.]
This is a known issue to be fixed in a future release of the core. To resolve the issue, please install the patches attached to this answer record as described below.
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
06/06/2016 - Initial release