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AR# 6717

CPLD 9500XL/XV/XPLA3 - How can I drive 5 volts from a 3.3V or 2.5V device? (Open Drain)

Description

Keywords: 9500XL, 9500XV, CPLD, CoolRunner, 3.3, 5, output, pull-up, pull up, collector

Some designs require a 3.3V CPLD core voltage (9500XL or CoolRunner XPLA3), and must have the ability to drive 0V to 5V outputs. Is there a method available to accomplish this? How can this be accomplished?

This solution does NOT apply to the CoolRunner-II device. For information on how to interface a CoolRunner-II to 5V, see (Xilinx XAPP429): "5V Tolerance Techniques for CoolRunner-II Devices."

解决方案

1

The basic strategy is to configure the I/O structure so that it drives either a 0 or is high-Z, and then use an external pull-up resistor (.5K to 1K) to 5V.

NOTE: Each function block can have only 5 unique Tristate Enables, this will limit the number of outputs that can drive 5V.

To do this, run the output signal logic to the enable of the OBUFT. The logic input of the OBUFT is connected to ground; this way, when the signal is low, the output is grounded.

When the signal is high, the output is put into a tristate condition, and the external pull-up will pull the output up to 5V.

Figure 1 - Open Drain/Collector Schematic
Figure 1 - Open Drain/Collector Schematic

2

The following expands upon the first solution. Using a feedback loop will allow the output to drive up to 3.3V (or 2.5V) for a short period of time before becoming 3-state and letting the external pull-up resistor take care of the rest. This has the advantage of having a faster rise from 0 to 3.3V (or 2.5V) than the first solution.

Figure 2 - Open Drain/Collector Schematic With Faster Rise
Figure 2 - Open Drain/Collector Schematic With Faster Rise


This is sample code for how to achieve the fast rise in VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
Port ( data : in std_logic; data_to_pin : inout std_logic);
end top;

architecture Behavioral of top is
begin
data_to_pin<= data when ((data and data_to_pin) ='0') else 'Z';
end Behavioral;

Code for Verilog:

module top(data, data_to_pin );
input data;
inout data_to_pin ;

assign data_to_pin = ((data & data_to_pin) == 0)? data : 1'bz;

endmodule
AR# 6717
创建日期 08/21/2007
Last Updated 12/19/2007
状态 Active
Type 综合文章