Some designs require a 3.3V CPLD core voltage (9500XL or CoolRunner XPLA3), and must have the ability to drive 0V to 5V outputs.
Is there a method available to accomplish this? How can this be accomplished?
This solution does NOT apply to the CoolRunner-II device.
The basic strategy is to configure the I/O structure so that it drives either a 0 or is high-Z, and then use an external pull-up resistor (.5K to 1K) to 5V.
Note: each function block can have only 5 unique 3-state Enables, this will limit the number of outputs that can drive 5V.
To do this, run the output signal logic to the enable of the OBUFT. The logic input of the OBUFT is connected to ground; this way, when the signal is low, the output is grounded.
When the signal is high, the output is put into a 3-state condition, and the external pull-up will pull the output up to 5V.
The following expands upon the first solution. Using a feedback loop will allow the output to drive up to 3.3V (or 2.5V) for a short period of time before becoming 3-state and letting the external pull-up resistor take care of the rest.
This has the advantage of having a faster rise from 0 to 3.3V (or 2.5V) than the first solution.
This is sample code for how to achieve the fast rise in VHDL:
Code for Verilog: