Version Found: v1.1 (Vivado 2016.1)
Version Resolved and other Known Issues: (Xilinx Answer 65751)
In the tactical patch attached to this answer record, the following fixes have been implemented:
1. pcie_cq_np_req tied to 2b11 from the user logic in the Xilinx example design in AXIST 512-bit mode. This is required to return correct credits.
2. Fixed logic to make sure pcie_cq_np_req_count provides correct NP credit received count in AXIST 512-bit mode.
3. Fixed logic related to cfg_msg fix where transmit message interface incorrectly generates two messages instead of one.
4. Fixed (Xilinx Answer 67144) for flgc2104 and flga2577 packages.
5. GUI options updated for straddle mode in AXIST 512-bit.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
These issues will be fixed in the next release of the core. Please install the patch in Vivado 2016.1 as described below:
06/20/2016 - Initial Release