2. 技术支持
  3. AR# 6733: Vitex BRAM VHDL simulation: setup violation on CLK A with respect to CLK B, or setup violation on CLKB with respect to CLK A
  4. AR# 67330: Zynq UltraScale+ MPSoC - PS DDR Pin Swap Guidelines

AR# 67330

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Zynq UltraScale+ MPSoC - PS DDR Pin Swap Guidelines

描述

Which pins can be swapped on a Zynq UltraScale+ PS DRAM interface?

解决方案

A byte lane includes any signals associated with the aligned 8-bits of DQ, such as DM, DQS, DQS_N, DBI and DQ signals.

Information on Zynq UltraScale+ PS DDR pin swapping can be found in (UG1075) - Zynq UltraScale+ MPSoC Packaging and Pinouts Product Specification

Note that additional pin swap restrictions are required if using the (infrequently used) Write CRC feature of DDR4. See (Xilinx Answer 68788) for the additional restrictions and how to enable the feature.

AR# 67330
日期 03/03/2017
状态 Active
Type 综合文章
器件
IP
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