AR# 67335

UltraScale/UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skipped

描述

Version Found: DDR4 v2.0 (Rev. 1), DDR3 v1.2 (Rev. 1), RLDRAM3 v1.2 (Rev. 1), QDRII+ v1.2 (Rev. 1), QDRIV v1.1 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

UltraScale+ Memory IP interfaces that are generated using a custom memory part will fail during opt_design if generation of the IP output products is skipped.

If generation of the IP output products is skipped, the following error message will occur:

ERROR: [Mig 66-99] Memory Core Error - [u_ddr3_0] MIG Instance port(s) c0_ddr3_addr[14],c0_ddr3_addr[15],c0_ddr3_ba[2],c0_ddr3_cas_n,c0_ddr3_we_n is/are not connected to top level instance of the design

解决方案

This error message is not intuitive and does not explain the reason for the failure. This will be addressed in a future release of Vivado.

To work around the issue, please generate the IP Output Products using the Global or Out-Of-Context (OOC) options.

Revision History:

06/06/2016 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 67335
日期 01/12/2018
状态 Active
Type 已知问题
器件 More Less
Tools
IP