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AR# 67392

UltraScale/UltraScale+ Memory IP - pulse width violations can occur

描述

Version Found: DDR4 v2.0 (Rev. 1), DDR3 v1.2 (Rev. 1), RLDRAM3 v1.2 (Rev. 1), QDRII+ v1.2 (Rev. 1), QDRIV v1.1 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

The UltraScale and UltraScale+ Memory IP incorrectly allows input clock frequencies greater than should be allowed, which can result in pulse width violations when checking timing.

解决方案

To prevent pulse width violations, ensure that the input clock frequency selected in the Memory IP GUI is within the supported range as defined in the DC and AC Switching Characteristics Data Sheet (DS923, DS922, DS893, DS892) for the target FPGA device.


DS923 Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
DS922 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics
DS893 Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
DS892 Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics

Revision History:

06/15/2016

AR# 67392
日期 01/12/2018
状态 Active
Type 已知问题
器件
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • Virtex UltraScale+
Tools
  • Vivado Design Suite - 2016.4
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.2
IP
  • MIG UltraScale
的页面