10G/25G Ethernet Subsystem logic simulation takes a long time to complete.
Is it possible to speed up the simulation?
The SIM_SPEED_UP option can be used to change the STARTUP_TIME and other timer settings, in order to speed up simulation.
Note: this change can be made only in simulation. For a design to work in hardware, do not define SIM_SPEED_UP.
VCS
Use the vlogan option +define+SIM_SPEED_UP
ModelSim
Use the vlog option +define+SIM_SPEED_UP
IES
Use the ncvlog option +define+SIM_SPEED_UP
Vivado Simulator:
Use the xvlog option -d SIM_SPEED_UP