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AR# 67548

ECO : Next Generation FPGA Editor


Engineering change orders (ECOs) are modifications to the post implementation netlist. The intention is to implement the changes with minimal impact to the original design.

The ECO flow is designed to handle use cases requiring the fastest possible turn-around such as modifying probes, fixing logic bugs, and bringing internal signals out of the device.



From 2016.1, Vivado officially supports the ECO flow in the GUI.

You can access the ECO GUI from the main menu, by selecting Layout > ECO.


2) ECO Toolbar / Scratch Pad

Once the ECO Layout is selected, the ECO Navigator is displayed on the left of the layout (A: highlighted in red in the above screen capture)

It provides access to netlist commands, run steps, report and analysis tools, and commands to save changes and generate programming files.

The Scratch Pad in the center of the layout (B: highlighted in Blue in the above screen capture) tracks netlist changes, as well as place and route status for cells, pins, ports, and nets.

The ECO toolbar contains controls for:

  • Netlist modifications
  • Place and route (Incremental)
  • Reports
  • Output files
  • Netlist connectivity
  • Placement and routing

3) ECO Flow Diagram

After Making the ECO modifications, Placement and Routing are entirely incremental.

Illegal modifications to the netlist can be made by the user, so Running Check ECO is encouraged.


4) Non - Basic Netlist Modification

The ECO Toolbar allows for basic netlist modification, advanced modification can be done by using manual TCL commands.

4-1) Adding a new module

The create_cell command cab be used to add cells to the netlist.

However, your reference should be an existing cell from the library or design source files.

If you want to add a new module, you can use following technique.

1) Synthesize the sub module, out of context, and write checkpoint ( for instance, clk_wiz_0.dcp)

2) Create a new cell referencing the new module as a black box:

create_cell -black_box INST_NAME -reference clk_wiz_0

3) replace the black box with the DCP:

read_checkpoint -cell INST_NAME clk_wiz_0.dcp
AR# 67548
日期 08/25/2016
状态 Active
Type 综合文章
  • Vivado Design Suite