AR# 67569

Zynq UltraScale+ MPSoC - 2016.2 FSBL Configuration Performs Degrades When XFSBL_PERF Mode Is Enabled

描述

I am trying to analyze / benchmark the boot performance of my Zynq UltraScale+ MPSoC device. When I enable the XFSBL_PERF mode to get debugging information, the performance numbers are slower than I expect.

解决方案

It is possible that the performance you are seeing is accurate. Please double-check the performance characteristics of your chosen boot device.

In other scenarios, the performance might be degraded due to the way in which the XFSBL_PERF mode is architected. 

In some places the XFSBL_PERF mode performs print() operations within the code it is benchmarking. This has a negative impact on configuration performance. To mitigate most of this, you can update the following #define values in xfsbl_debug.h:

#define DEBUG_INFO          (0x00000000U)    /* More debug information */
#define DEBUG_DETAILED          (0x00000000U)    /* More debug information */

By setting these constants to 0x0, the additional print statements are disabled and the performance of the configuration is impacted as little as possible while still providing useful debug information.

AR# 67569
日期 08/18/2016
状态 Active
Type 综合文章
器件
Tools