AR# 67629

SMPTE SD/HD/3G-SDI v3.0 - XAPP1290 - When using the XAPP1290 reference design, I cannot see the Color Bar when using CPLL

描述

After I change the GT type to CPLL when using the XAPP1290 reference design, I cannot see the Color Bar. 

How can I fix this problem?

解决方案

For the UltraScale+ GTH/GTY CPLL, the CPLL calibration block should be used to ensure that the CPLL locks reliably and acquires the correct frequency.

This calibration block is not generated in the GT wizard by default. This will be enabled automatically by the Wizard from Vivado 2017.2 on.

For versions prior to 2017.2, You will need to enable it manually by setting C_INCLUDE_CPLL_CAL to 1:

create_property C_INCLUDE_CPLL_CAL cell -type int
set_property C_INCLUDE_CPLL_CAL 1 [get_cells {*/genblk1[0].sdi_wrapper_support/sdi_wrapper/smpte_3gsdi_gtwiz_i/inst}]

For more details on this issue, please refer to (Xilinx Answer 67320)

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
67320 Kintex/Virtex/Zynq UltraScale+ MPSoC: Incorrect GTH/GTY CPLL Frequency N/A N/A
AR# 67629
日期 06/21/2017
状态 Active
Type 综合文章
IP