描述

When DDR ECC is enabled and multiple read/modify/write (RMW) transactions are issued to the DDR controller, a collision between read and write channels might cause video class traffic to underrun.

This issue is caused when a read and write to the same cacheline using smaller burst sizes trigger a RMW transaction in both directions, slowing the controller and potentially missing its video class latency requirements.

解决方案

Work-arounds:

• Disable ECC
• Mark the PS DDR as not device memory
  
• Increase the burst size that the active masters issue to the PS DDR to be the burst size of the DRAM interface to prevent RMW cycles.

This behavior will be documented in a future version of (UG1085) Zynq UltraScale+ Technical Reference Manual, currently planned for v1.6.

The proposed TRM text is as follows:

'Enabling ECC on the DDR can diminish overall available memory bandwidth or increase access latency under certain conditions. System designers should carefully consider the tradeoffs between enabling ECC and bandwidth / latency requirements of other components in the system, when there is a possibility of a significant amount of partial (sub-64 bit) writes to memory.'