AR# 67871

Zynq UltraScale+ MPSoC: MicroBlaze PMU MDM is disabled by default on ES2 and higher.

描述

On Zynq UltraScale+ devices with silicon revision versions higher than 1.0, I do not see the MicroBlaze Performance Monitor unit (PMU) in the XSDB target list.

1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU
9* Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (Power On Reset)
12 Cortex-A53 #3 (Power On Reset)

How can I debug the PMU firmware?

解决方案

In order to debug the PMU Firmware on ES2 silicon and higher, the security gate to access the MicroBlaze PMU MicroBlaze Debug Module (MDM) needs to be released by writing CSU.jtag_sec{sss_pmu_sec} to all ones.

Option 1 - by writing the register directly

xsct% targets -set -filter {name =~ "PSU"}
xsct% mwr 0xffca0038 0x1FF

Option 2 - by using a dedicated XSCT command.

xsct% targets -set -filter {name =~ "PSU"}
xsct% disable_pmu_gate

 
xsct% targets
1 PS TAP
2 PMU
13 MicroBlaze PMU (Sleeping. No clock)
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU
9* Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (Power On Reset)
12 Cortex-A53 #3 (Power On Reset)
AR# 67871
日期 07/27/2017
状态 Active
Type 综合文章
器件