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AR# 67946

Vivado Synthesis - Using VHDL configuration without the component instantiation statement is not supported

描述

When I use a VHDL configuration similar to the following, Vivado Synthesis returns an error.

Example code:

architecture arch of top is
begin
  U : configuration work.mycfg port map (
                                        din => din,
                                        dout => dout
                                      );
end arch;

Error message:

ERROR: [Synth 8-5826] no such design unit 'mycfg' in library 'work' [xxxxxx/top.vhd:31].

解决方案

Using a VHDL configuration without the component instantiation statement is not supported.

The supported coding style is as follows:


architecture arch of top is
component cfg_comp 
  port (
        din : in std_logic_vector(1 downto 0);
        dout : out std_logic_vector(1 downto 0)
       );
end component;      
for U : cfg_comp use configuration work.mycfg;              

begin
  U : cfg_comp port map (
                                        din => din,
                                        dout => dout
                                      );
end arch;


The complete code example is attached in this Answer Record.

附件

文件名 文件大小 File Type
67946_code_example.zip 1 KB ZIP
AR# 67946
日期 10/13/2016
状态 Active
Type 综合文章
Tools
  • Vivado Design Suite
的页面