Version Found: DDR4/3 v2.1; QDRII+ v1.3; RLD3 v1.3; QDRIV v1.2
Version Resolved: See (Xilinx Answer 58435)
When using the wizard feature to "Specify MMCM M and D on Advanced Clocking Page to calculate Ref Clk reference input clock speed (ps)" the following DRC messages might be seen when running the IP through implementation and BitGen:
Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range of 10.000000 Mhz to 550.000000 Mhz set by CLKPFD_FREQ_MIN/MAX. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance sim_tb_top.u_example_top.u_rld3_0_mcs_ecc_dis.inst.u_rld3_infrastructure.gen_mmcme3.u_mmcme_adv_inst
[DRC 23-20] Rule violation (PDRC-167) MMCM_adv_ClkFreqPFD_div_no_dclk - The computed value 799.361 MHz (CLKIN1_PERIOD, net xlnx_opt_) for the PFD operating frequency of the MMCME3_ADV site MMCME3_ADV_X0Y1 (cell u_rld3_0_mcs_ecc_dis/inst/u_rld3_infrastructure/gen_mmcme3.u_mmcme_adv_inst) falls outside the operating range of the MMCM PFD frequency for this device (10.000 - 550.000 MHz). The computed value is (1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (1.251000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a PFD frequency within the rated operating range for this device, or try re-running the Timing Engine.
The tool is currently not limiting selection to correct M and D values only.
To work around this, use a different combination of M, D, and D0 values to avoid this error. In doing so, you must ensure that CLKIN/D >= 70MHz.