Some designs created in the 2016.1 and 2016.2 versions of Xilinx Design Tools have been found to have incorrect bitstreams. The root cause has been identified as a multi-threading (default) issue in write_bitstream, which can cause some configuration memory cells to be set to 0 instead of 1.
CRC will still pass for these bitstreams, as the bitstream CRC is calculated using the incorrectly set values and will result in a valid check when the bitstream is loaded.
All devices (7 Series, Zynq-7000, UltraScale, UltraScale+, and Zynq UltraScale+) and all OS's (Windows and Linux) are impacted by this issue.
Xilinx Design Tools including Vivado, SDAccel, and SDSoC (2016.1 and 2016.2 versions) are impacted.
Multi-threading is turned off for write_bitstream in Vivado 2016.3, SDAccel 2016.3 and SDSoC 2016.3, so this issue will not occur for those versions and later.
New designs using Vivado, SDAccel or SDSoC 2016.1 or 2016.2 must be generated with the instructions below. Alternatively, you can update to Xilinx Design Tools 2016.3, where multi-threading for write_bitstream is turned off.
Permanently force the use of a single thread during bitstream generation with any 2016.1 or 2016.2 Xilinx Design Tool releases by adding the following Tcl command to the init.tcl script:
Note: This command only sets write_bitstream to use a single thread. It does not affect other processes.
Additional information on init.tcl:
When you start the Xilinx Design tools, it looks for the init.tcl initialization script in two different locations:
1) In the software installation: installdir/Vivado/version/scripts/init.tcl
installdir is the installation directory where the Vivado Design Suite is installed.
2) In the local user directory:
If init.tcl exists in both of these locations, Vivado sources the file from the installation directory first, and then from your home directory.
For more information, see the Loading and Running Tcl Scripts chapter in (UG894) Vivado Design Suite User Guide Using Tcl Scripting.
Existing bitstreams created in Vivado, SDAccel or SDSoC 2016.1 or 2016.2 can be verified for correctness by regenerating the bitstream using a single thread, and doing a comparison.
A Tcl script called AR68006.tcl is attached to this Answer Record, and can be used to regenerate the bitstream with a single thread, and do the comparison.
NOTE: Ensure that the same Xilinx Design Tool release that was used to generate xxOLD.bit is used to run the AR68006.tcl script that generates NEW.bit
- Additionally, If using 2016.1 please ensure that the same OS that was used to generate xxOLD.bit is used to run the AR68006.tcl script that generates NEW.bit.
1) Download the attached script, 'AR68006.tcl'.
2. From the Tcl command line enter the following command:
vivado -mode batch -source AR68006.tcl -tclargs xxOLD.dcp xxOLD.bit ConfigMode elfFileName