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FPGA Express 3.2: Pullup/pulldown/keeper for Virtex are incorrectly written to the netlist
Keywords: FPGA Express, pullup, pulldown, keeper, Virtex, netlist
When you instantiate a Pullup or Keeper for input port, FPGA Express version 3.1
connects it after IBUF instead of before IBUF. Consequently, M1 mapper
optimizes them away.
This problem has gone away in FPGA Express version 3.4.
1 Use EPIC/FPGA Editor to insert desired component in the IOB.
2 Use a temporary signal to connect the Pullup, then connect this signal to the
input. This solution does not work for the Keeper component.
Sample VHDL code:
entity pullvhd is
port (A1, A2 : in std_logic;
B : out std_logic);
architecture RTL of pullvhd is
port (O : out STD_LOGIC);
signal temp : std_logic;
temp <= A1;
B <= A1 and A2;
U1: PULLUP port map (O => temp);
Sample Verilog code:
module pullv (A1, A2, B);
input A1, A2;
PULLUP U1 (.o(temp));
assign temp = A1;
assign B = A1 & A2;